This invention relates in general to a system for providing an improved Advanced Peripheral Bus, and more particularly to system for providing an improved synchronous operation of an advanced peripheral bus with backward compatibility.
The Advanced Microcontroller Bus Architecture (AMBA) specification defines an on-chip communications standard for designing high-performance embedded microcontrollers. Three distinct buses are defined within the AMBA specification: an Advanced High-performance Bus (AHB), an Advanced System Bus (ASB), and an Advanced Peripheral Bus (APB).
The AMBA AHB is for high-performance, high clock frequency system modules. The AHB acts as the high-performance system backbone bus. AHB supports the efficient connection of processors, on-chip memories and off-chip external memory interfaces with low-power peripheral macrocell functions. AHB is also specified to ensure ease of use in an efficient design flow using synthesis and automated test techniques.
The AMBA ASB is for high-performance system modules. AMBA ASB is an alternative system bus suitable for use where the high-performance features of AHB are not required. ASB also supports the efficient connection of processors, on-chip memories and off-chip external memory interfaces with low-power peripheral macrocell functions.
The AMBA APB is for low-power peripherals. AMBA APB is optimized for minimal power consumption and reduced interface complexity to support peripheral functions. APB can be used in conjunction with either version of the system bus.
An AMBA-based microcontroller typically consists of a high-performance system backbone bus (AMBA AHB or AMBA ASB), able to sustain the external memory bandwidth, on which the CPU, on-chip memory and other Direct Memory Access (DMA) devices reside. This bus provides a high-bandwidth interface between the elements that are involved in the majority of transfers. Also located on the high-performance bus is a bridge to the lower bandwidth APB, where most of the peripheral devices in the system are located (see FIG. 1).
The APB provides the basic peripheral macrocell communications infrastructure as a secondary bus from the higher bandwidth pipelined main system bus. Such peripherals typically have interfaces which are memory-mapped registers, have no high-bandwidth interfaces, and are accessed under programmed control. The external memory interface is application-specific and may only have a narrow data path, but may also support a test access mode which allows the internal AMBA AHB, ASB and APB modules to be tested in isolation with system-independent test sets.
AHB is a later generation of AMBA bus which is intended to address the requirements of high-performance synthesizable designs. It is a high-performance system bus that supports multiple bus masters and provides high-bandwidth operation. The AHB implements the features required for high-performance, high clock frequency systems including burst transfers, split transactions, single-cycle bus master handover, single-clock edge operation, non-tristate implementation, and wider data bus configurations (64/128 bits). Bridging between this higher level of bus and the current ASB/APB can be done efficiently to ensure that any existing designs can be easily integrated.
An AHB design may contain one or more bus masters, typically a system would contain at least the processor and test interface. However, it would also be common for a Direct Memory Access (DMA) or Digital Signal Processor (DSP) to be included as bus masters. The external memory interface, APB bridge and any internal memory are the most common AHB slaves. Any other peripheral in the system could also be included as an AHB slave. However, low-bandwidth peripherals typically reside on the APB.
A typical AHB system design contains the following components: an AHB master, an AHB slave, an AHB arbiter, and an AHB decoder. A bus master is able to initiate read and write operations by providing an address and control information. Only one bus master is allowed to actively use the bus at any one time. A bus slave responds to a read or write operation within a given address-space range. The bus slave signals back to the active master the success, failure or waiting of the data transfer. The bus arbiter ensures that only one bus master at a time is allowed to initiate data transfers. Even though the arbitration protocol is fixed, any arbitration algorithm, such as highest priority or fair access can be implemented depending on the application requirements. An AHB would include only one arbiter, although this would be trivial in single bus master systems. The AHB decoder is used to decode the address of each transfer and provide a select signal for the slave that is involved in the transfer. A single centralized decoder is required in all AHB implementations.
A typical ASB system may contain one or more bus masters. For example, at least the processor and test interface. However, it would also be common for a Direct Memory Access (DMA) or Digital Signal Processor (DSP) to be included as bus masters. The external memory interface, APB bridge and any internal memory are the most common ASB slaves. Any other peripheral in the system could also be included as an ASB slave. However, low-bandwidth peripherals typically reside on the APB.
An ASB system design typically contains the following components: an ASB master, an ASB slave, an ASB decoder, and an ASB arbiter. A bus master is able to initiate read and write operations by providing an address and control information. Only one bus master is allowed to actively use the bus at any one time. A bus slave responds to a read or write operation within a given address-space range. The bus slave signals back to the active master the success, failure or waiting of the data transfer. The bus decoder performs the decoding of the transfer addresses and selects slaves appropriately. The bus decoder also ensures that the bus remains operational when no bus transfers are required. A single centralized decoder is required in all ASB implementations. The bus arbiter ensures that only one bus master at a time is allowed to initiate data transfers. Even though the arbitration protocol is fixed, any arbitration algorithm, such as highest priority or fair access can be implemented depending on the application requirements. An ASB would include only one arbiter, although this would be trivial in single bus master systems.
The APB is part of the AMBA hierarchy of buses and is optimized for minimal power consumption and reduced interface complexity. The APB appears as a local secondary bus that is encapsulated as a single AHB or ASB slave device. APB provides a low-power extension to the system bus which builds on AHB or ASB signals directly. The APB bridge appears as a slave module which handles the bus handshake and control signal retiming on behalf of the local peripheral bus. By defining the APB interface from the starting point of the system bus, the benefits of the system diagnostics and test methodology can be exploited. The APB is typically used to interface to any peripherals which are low bandwidth.
An APB implementation typically contains a single APB bridge which is required to convert AHB or ASB transfers into a suitable format for the slave devices in the APB. The bridge provides latching of all address, data and control signals, as well as providing a second level of decoding to generate slave select signals for the APB peripherals. All other modules on the APB are APB slaves. The APB slaves have the following interface specification: address and control valid throughout the access (unpipelined), zero-power interface during non-peripheral bus activity (peripheral bus is static when not in use), timing can be provided by decode with strobe timing (unclocked interface), and write data valid for the whole access (allowing glitch-free transparent latch implementations).
The AHB signal list is described below in Table 1. All signals are prefixed with the letter H, ensuring that the AHB signals are differentiated from other similarly named signals in a system design.
An AHB also has a number of signals required to support multiple bus master operation (see Table 2). Many of these arbitration signals are dedicated point to point links and in Table 2 the suffix x indicates the signal is from module X. For example, there will be a number of HBUSREQx signals in a system, such as HBUSREQarm, HBUSREQdma and HBUSREQtic.
All AMBA APB signals use the single letter P prefix. Some APB signals, such as the clock, may be connected directly to the system bus equivalent signal. Table 4 shows the list of AMBA APB signal names, along with a description of how each of the signals is used.
The APB operation can be described using the following: a state diagram, write transfer operation, and a read transfer operation. The state diagram, shown in FIG. 2, can be used to represent the activity of the peripheral bus. Operation of the state machine is through the three states: Idle, Setup, and Enable. The Idle is the default state for the peripheral bus. The Setup state occurs when a transfer is required. The bus moves into the setup state from the Idle state, where the appropriate select signal, PSELx, is asserted. The bus only remains in the setup state for one clock cycle and will always move to the enable state on the next rising edge of the clock.
In the enable state the enable signal, PENABLE is asserted. The address, write and select signals all remain stable during the transition from the setup to enable state. The enable state also only lasts for a single clock cycle and after this state the bus will return to the idle state if no further transfers are required. Alternatively, if another transfer is to follow then the bus will move directly to the setup state. It is acceptable for the address, write and select signals to glitch during a transition from the enable to setup states.
The basic write transfer is shown in FIG. 3. The write transfer starts with the address, write data, write signal and select signal all changing after the rising edge of the clock. The first clock cycle of the transfer is called the setup cycle. After the following clock edge the enable signal PENABLE is asserted, and this indicates that the enable cycle is taking place. The address, data and control signals all remain valid throughout the enable cycle. The transfer completes at the end of this cycle. The enable signal, PENABLE, will be de-asserted at the end of the transfer. The select signal will also go LOW, unless the transfer is to be immediately followed by another transfer to the same peripheral. In order to reduce power consumption the address signal and the write signal will not change after a transfer until the next access occurs. The protocol only requires a clean transition on the enable signal. It is possible that in the case of back to back transfers the select and write signals may glitch.
FIG. 4 shows a read transfer. The timing of the address, write, select and strobe signals are all the same as for the write transfer. In the case of a read, the slave must provide the data during the enable cycle. The data is sampled on the rising edge of clock at the end of the enable cycle. The APB bridge is the only bus master on the APB. In addition, the APB bridge is also a slave on the higher-level system bus. FIG. 5 shows the APB signal interface of an APB bridge. The bridge unit converts system bus transfers into APB transfers and performs the following functions: latches the address and holds it valid throughout the transfer, decodes the address and generates a peripheral select, PSELx. Only one select signal can be active during a transfer, drives the data onto the APB for a write transfer, drives the APB data onto the system bus for a read transfer, and generates a timing strobe, PENABLE, for the transfer.
APB slaves have a simple, yet flexible, interface. The exact implementation of the interface will be dependent on the design style employed and many different options are possible. FIG. 6 shows the signal interface of an APB slave. The APB slave interface is very flexible. For a write transfer the data can be latched at the following points: on either rising edge of PCLK, when PSEL is HIGH and on the rising edge of PENABLE, when PSEL is HIGH. The select signal PSELx, the address PADDR and the write signal PWRITE 902 can be combined to determine which register should be updated by the write operation. For read transfers the data can be driven on to the data bus when PWRITE 902 is LOW and both PSELx and PENABLE are high.
Interfacing the APB to the AHB is comprises read transfers operations, write transfers operations, back to back transfers operation, and tristate data bus implementations. FIG. 7 illustrates a read transfer. The transfer starts on the AHB at time T1 and the address is sampled by the APB bridge at T2. If the transfer is for the peripheral bus then this address is broadcast and the appropriate peripheral select signal is generated. This first cycle on the peripheral bus is called the setup cycle, this is followed by the enable cycle, when the PENABLE signal is asserted. During the enable cycle the peripheral must provide the read data. Normally it will be possible to route this read data directly back to the AHB, where the bus master can sample it on the rising edge of the clock at the end of the enable cycle, which is at time T4 in FIG. 7.
The above definition of the APB bus possesses a few deficiencies when used in higher-data throughput environments. One of the modules on an AHB bus of a system is a DMA controller. Typically, a DMA controller will transfer data one data block per clock cycle in a contiguous block of data. From the timing for the APB bus, a data transfer requires two clock cycles within the operation of the APB bus. Therefore, the AHB bus side of the system will operate with a data rate of twice the rate of the APB bus. This fact limits the data throughput from an AHB side of a system to an APB side of a system. Additionally, the APB bus is defined to transfer a 32 bit word during each read or write operation. This fact also limits the flexibility of the data transfer system for data between devices on the AHB side of a system and a APB side of a system.
Finally, the above definition of the APB bus utilizes the non-continuous signal PENABLE to latch data transfers into APB slave devices. Systems which utilize advanced test methodologies typically use synchronous designs with all logic events occurring relative to a continuous clock signal. At the same time, the power consumed by peripheral devices is highly dependent upon the clock rate for the system clock used to control the operation of the peripheral devices. Because the peripheral devices are typically designed to be lower-power devices, the clock controlling its operation needs to be a slow as possible. The use of the highest speed clock PCLK that matches the high speed BCLK signal would lead to excessive power consumption for peripheral devices.
To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a system for providing an improved synchronous operation of an advanced peripheral bus with backward compatibility.
The present invention solves the above-described problems by providing an electronic bridge apparatus for providing a first electronic device attached to a high-data throughput bus and a second electronic device attached to a lower-speed peripheral bus. The electronic bridge apparatus comprises an input bus circuit for receiving a plurality of input bus signals from the high-data throughput bus, the plurality of input bus signals comprise a multi-bit system data bus and a multi-bit system address bus and an input control signal circuit for receiving a plurality of input control signals from the high-data throughput bus, the plurality of input control signals comprises a continuous input BCLK clock signal. The bridge further comprises an output bus circuit for generating a plurality of output bus signals onto the lower-speed peripheral bus, the plurality of output bus signals comprise a multi-bit peripheral data bus and a multi-bit peripheral address bus, an output size signal circuit for generating one or more output size signals for indicating the number of bits being used for a data transfer over the multi-bit peripheral data bus, and an output control signal circuit for generating a plurality of output control signals onto the lower-speed peripheral bus. The plurality of output control signals comprise a PWRITE 902 write control signal for indicating whether a write operation is occurring, a continuous PCLK signal 903 having a rising edge and a falling edge for controlling the transfer of data over the lower-speed peripheral bus, and one or more PSELx signals for indicating the particular cycle of the PCLK signal 903 in which data is to be transferred over the lower-speed peripheral bus. Data is transferred into the second electronic device over the multi-bit peripheral data bus on the rising edge of the PCLK signal 903 during a clock cycle when the PSELx signal 904 is in an active state and the PWRITE signal 902 is in an active state.
Another aspect of the present invention is a slave apparatus for transferring digital data from a first electronic device attached to a high-data throughput bus through an electronic bridging device to a lower-speed peripheral bus. The slave apparatus comprises an input bus circuit for receiving a plurality of output bus signals from the lower-speed peripheral bus, the plurality of output bus signals comprise a multi-bit peripheral data bus and a multi-bit peripheral address bus, an input size signal circuit for receiving one or more output size signals for indicating the number of bits being used for a data transfer over the multi-bit peripheral data bus, and an input control signal circuit for receiving a plurality of input control signals from the lower-speed peripheral bus. The plurality of input control signals comprise a PWRITE write control signal 902 for indicating whether a write operation is occurring, a continuous PCLK clock signal having a rising edge and a falling edge for controlling the transfer of data over the lower-speed peripheral bus, and one or more PSELx signals for indicating the particular cycle of the PCLK signal in which data is to be transferred over the lower-speed peripheral bus. Data is transferred into the slave apparatus over the multi-bit peripheral data bus on the rising edge of the PCLK signal during a clock cycle when the PSELx signal is in an active state and the PWRITE signal 902 is in an active state.
These and various other advantages and features of novelty which characterize the invention are pointed out with particularity in the claims annexed hereto and form a part hereof. However, for a better understanding of the invention, its advantages, and the objects obtained by its use, reference should be made to the drawings which form a further part hereof, and to accompanying descriptive matter, in which there are illustrated and described specific examples of an apparatus in accordance with the invention.